1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device and more particularly, to a method of fabricating a so-called Metal-Insulator-Semiconductor Field-Effect Transistor (MISFET) on a semiconductor substrate.
2. Description of the Prior Art
Conventionally, a silicon dioxide (SiO.sub.2) film was popularly used as a gate insulator of a MISFET, because a SiO.sub.2 film has a good insulation property, a good reliability characteristic, and a low interface-trap density. In this case, a MISFET is, for example, fabricated in the following way.
First, as shown in FIG. 1A, an isolation region 102 is formed on a main surface of an n- or p-type single-crystal silicon (Si) substrate 101 by a selective oxidation process, i.e., LOCal Oxidation of Silicon (LOCOS) process. Then, a silicon dioxide (SiO.sub.2) film 108 is formed on the exposed surface of the substrate 101 by a thermal oxidation process.
Subsequently, as shown in FIG. 1B, a gate electrode 105 is formed on the SiO.sub.2 film 108. Then, a pair of sidewall spacers 106 are formed on the SiO.sub.2 film 108 at each side of the gate electrode 105. The pair of sidewall spacers 106 are usually made of SiO.sub.2.
Using the isolation region 102, the gate electrode 105, and the pair of sidewall spacers 106 as a mask, a p-type dopant such as boron (B) or an n-type dopant such as arsenic (As) is selectively ion-implanted into the surface area of the substrate 101 through the SiO.sub.2 film 106 according to the conductivity type of the substrate 101. Thus, a pair of p- or n-type source/drain regions 107 are formed in the substrate 101 at each side of the gate electrode 105, as shown in FIG. 1C.
Since the p- or n-type dopant is implanted into the gate electrode 105 also during the above ion-implantation process, the ion-implanted gate electrode is denoted by a reference numeral 105a in FIG. 1C.
Finally, the substrate 101 is subjected to a heat treatment to activate or anneal the dopant atoms implanted into the substrate 101 during the step of forming the pair of source/drain regions 107.
Thus, a p- or n-channel MISFET is formed on the n- or p-type single-crystal silicon substrate 101 by the pair of source/drain regions 107, the SiO.sub.2 film 108, and the gate electrode 105a. The part of the SiO.sub.2 film 108 located just below the gate electrode 105a serves as a gate insulator of the MISFET.
In recent years, to further miniaturize a MISFET and to improve its performance, a gate insulator film has been required to be thinner. To cope with this requirement, p-type polycrystalline silicon (i.e., polysilicon) has been often used for forming a gate electrode in p-type MISFETs. P-type polysilicon has been usually fabricated by doping a p-type dopant, popularly boron (B), into undoped polysilicon.
When the gate electrode 105a is made of boron-doped polysilicon in the conventional method shown in FIGS. 1A to 1C, the following problem tends to occur.
Specifically, during the heat-treatment process for activating or annealing the dopant atoms implanted into the substrate 101, boron atoms doped into the gate electrode 105a tend to penetrate through the SiO.sub.2 film 108 and then, the boron atoms that have penetrated through the SiO.sub.2 film 108 are diffused into the part 101a of the substrate 101 just below the SiO.sub.2 film 108 between the pair of source/drain regions 107. The part 101a of the substrate 101 is called the "channel region". The diffused boron atoms into the channel region 101a will fluctuate or deviate the threshold voltage of the MISFET.
The penetration of the boron atoms through the gate insulator film 108 has been termed the "boron penetration" phenomenon.
To prevent the "boron penetration" phenomenon from occurring, an improvement where a SiO.sub.2 film doped with nitrogen (N) (i.e., nitrogen-doped SiO.sub.2) is used as a gate insulator film was developed, which was reported in the paper, 1996 IEDM Technical Digest, page 331-334, written by C. Lin et al., and entitled "Leakage Current, Reliability Characteristics, and Boron Penetration of Ultra-Thin (32-36A) O.sub.2 -Oxides and N.sub.2 O/NO Oxynitrides".
However, this improvement has the following problems.
First, nitrogen-doped SiO.sub.2 is used for forming a gate insulator film and therefore, the mobility of a carrier in the channel region 101a is lower than the case where undoped SiO.sub.2 is used for forming a gate insulator film. Consequently, the performance of the MISFET degrades.
Second, to prevent the boron penetration phenomenon, the doping concentration of nitrogen of a nitrogen-doped SiO.sub.2 film needs to be increased with the decreasing thickness of a gate insulator film. For example, if a gate insulator film is as thin as approximately 3 nm or less, the doping concentration of nitrogen of a nitrogen-doped SiO.sub.2 film needs to be 10 atomic percents (at %) or higher. However, this is very difficult to be realized because of the following reason.
Specifically, a nitrogen-doped SiO.sub.2 film is usually formed by heat-treating an undoped SiO.sub.2 film in an atmosphere containing nitrogen oxide (i.e., NO or N.sub.2 O). Therefore, an undoped SiO.sub.2 film is not only doped with nitrogen but also oxidized in this heat-treatment process. This oxidation unavoidably increases the thickness of a resultant nitrogen-doped SiO.sub.2 film. As a result, it is not easy to increase the doping concentration of nitrogen of a nitrogen-doped SiO.sub.2 film up to 10 at % or higher by the above heat-treatment process. This means that if a gate insulator film is as thin as approximately 3 nm or less, it is difficult to prevent the boron penetration phenomenon with the use of the nitrogen-doped SiO.sub.2 film.
Moreover, technique where silicon nitride (SiN.sub.x) isused for forming a gate insulator film instead of undoped SiO.sub.2 has been known, which was disclosed, for example, in the Japanese Non-Examined Patent Publication No. 59-172729 published in 1984. This technique, however, has a problem that the subthreshold characteristics of a MISFET degrade, because the trap density at the interface between a silicon nitride film and a single-crystal silicon substrate is high.